[200:356342846]SDPE[2] card_boot_start
FPGA_STATUS:FACTORY
[02][0][ENDOR_R2]ed01ffff:32000000
[02][1][ENDOR_R2]ed02ffff:42010000
[200:356527167]##############BOARD HW BOOT
[200:356619328]##############BOARD CALIBRATING
[200:356637760]##############LANE SLOT ENABLE NOT AVAILABLE
[200:356656192]CARBON_UHD[2] START PMA INIT UNDI:18 FCL:6 C2C:54
[200:356693057]CARBON_UHD[2]  UNDI:18 FCL:6 C2C:54
[200:356729921]do_card_boot_pma_init CARBON_UHD[2] set_undi_xcvr_mode
[200:356748353]set_fcb_undi_xcvr_data_mode[2]board_undi_chans:18
[200:357190725]set_fcb_undi_xcvr_data_mode out
[200:357209157]do_card_boot_pma_init CARBON_UHD[2]set_board_undi_xcvr_data_mode 
[200:357246021]set_board_undi_xcvr_data_mode[2] CARBON_UHD:chans:undi:18
[200:358186062]set_board_undi_xcvr_data_mode[2] CARBON_UHD: out r=0
[200:358222926]do_card_boot_pma_init CARBON_UHD[2]set_fcl_igr_mode 
[200:358241358]set_fightclub_igr_eyeq_mode[2] frame FCL chans:16
[200:358683730]set_fightclub_igr_eyeq_mode out
[200:358702162]do_card_boot_pma_init CARBON_UHD[2] set_fcl_egr_mode
[200:358739026]set_fightclub_egr_eyeq_mode[2] BOARD FCL chans:6
[200:358923348]set_fightclub_egr_eyeq_mode out
[200:358941780]set_c2c_eyeq_mode[2]board_c2c_chans:54
[200:361983087]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) INGRESS
[200:362019951]setup_board_fcl_fpga_xcvr_pma[2] CARBON_UHD:chans:fcl:6
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 40 fcl igr tx 00 vod 31 pre1 00 pre2 00 post1 00 post2 00 
[200:372231368]ultrix_2ns_set_fcl_S5_pma_rx [2][0] fcl igr rx 00
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  5 fcl igr rx 00 rx_dc 03 rx_eq 08
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 24 fcl igr tx 02 vod 31 pre1 00 pre2 00 post1 00 post2 00 
[200:392635770]ultrix_2ns_set_fcl_S5_pma_rx [2][2] fcl igr rx 02
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  3 fcl igr rx 02 rx_dc 03 rx_eq 11
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 13 fcl igr tx 03 vod 28 pre1 -6 pre2 00 post1 06 post2 02 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 12 fcl igr tx 04 vod 31 pre1 -4 pre2 00 post1 -1 post2 00 
[200:423214724]ultrix_2ns_set_fcl_S5_pma_rx [2][4] fcl igr rx 04
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  1 fcl igr rx 04 rx_dc 02 rx_eq 13
[200:433407708]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) EGRESS 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 41 fcl egr rx 00 dc 00 ac 10 vga 07 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  5 fcl egr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 29 fcl egr rx 02 dc 00 ac 12 vga 07 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  3 fcl egr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 17 fcl egr rx 03 dc 00 ac 06 vga 05 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 13 fcl egr rx 04 dc 00 ac 14 vga 02 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  1 fcl egr tx 04 tx_vod 30 tx_pe0 -4 tx_pe1 01 tx_pe2 00 
[200:504666441]setup_board_fcl_fpga_xcvr_pma[2] CARBON_UHD: out r=0
[200:504703305]setup_board_c2c_fpga_xcvr_pma[2] CARBON_UHD:chans:c2c:6
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 19 c2c tx 00 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 26 c2c rx 00 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 21 c2c tx 01 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 22 c2c rx 01 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 20 c2c tx 02 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 24 c2c rx 02 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 22 c2c tx 03 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 20 c2c rx 03 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 23 c2c tx 04 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 19 c2c rx 04 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  2 c2c tx 05 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 14 c2c rx 05 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  0 c2c tx 06 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 37 c2c rx 06 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  5 c2c tx 07 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 21 c2c rx 07 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  3 c2c tx 08 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 33 c2c rx 08 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  4 c2c tx 09 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 32 c2c rx 09 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  7 c2c tx 10 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 31 c2c rx 10 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 32 c2c tx 11 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  3 c2c rx 11 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  1 c2c tx 12 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 39 c2c rx 12 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  9 c2c tx 13 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 34 c2c rx 13 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn  8 c2c tx 14 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 25 c2c rx 14 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 11 c2c tx 15 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 30 c2c rx 15 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 10 c2c tx 16 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 27 c2c rx 16 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 33 c2c tx 17 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  6 c2c rx 17 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 13 c2c tx 18 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 36 c2c rx 18 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 14 c2c tx 19 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 38 c2c rx 19 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 15 c2c tx 20 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 35 c2c rx 20 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 16 c2c tx 21 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 29 c2c rx 21 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 17 c2c tx 22 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 28 c2c rx 22 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 29 c2c tx 23 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 10 c2c rx 23 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 28 c2c tx 24 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 12 c2c rx 24 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 27 c2c tx 25 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 13 c2c rx 25 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 26 c2c tx 26 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 16 c2c rx 26 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 25 c2c tx 27 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 18 c2c rx 27 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 35 c2c tx 28 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  0 c2c rx 28 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 34 c2c tx 29 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  4 c2c rx 29 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 41 c2c tx 30 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn 11 c2c rx 30 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 31 c2c tx 31 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  7 c2c rx 31 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 39 c2c tx 32 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  8 c2c rx 32 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 38 c2c tx 33 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  5 c2c rx 33 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 37 c2c tx 34 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  2 c2c rx 34 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  0 blk 10 chn 36 c2c tx 35 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  1 blk 10 chn  1 c2c rx 35 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 28 c2c tx 36 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 12 c2c rx 36 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 26 c2c tx 37 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 18 c2c rx 37 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 22 c2c tx 38 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 21 c2c rx 38 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 27 c2c tx 39 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 14 c2c rx 39 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 24 c2c tx 40 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 17 c2c rx 40 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 40 c2c tx 41 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  2 c2c rx 41 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 20 c2c tx 42 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 24 c2c rx 42 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 14 c2c tx 43 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 27 c2c rx 43 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 35 c2c tx 44 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  5 c2c rx 44 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 18 c2c tx 45 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 25 c2c rx 45 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 16 c2c tx 46 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 26 c2c rx 46 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  2 c2c tx 47 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 39 c2c rx 47 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 12 c2c tx 48 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 30 c2c rx 48 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 10 c2c tx 49 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 33 c2c rx 49 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  8 c2c tx 50 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 35 c2c rx 50 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 32 c2c tx 51 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  8 c2c rx 51 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 30 c2c tx 52 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  9 c2c rx 52 dc 00 ac 14 vga 04 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 33 c2c tx 53 vod 28 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 11 c2c rx 53 dc 00 ac 14 vga 04 
[201:605840569]setup_board_c2c_fpga_xcvr_pma[2] CARBON_UHD: out r=0
[201:605859001]setup_board_undi_fpga_xcvr_pma[2] CARBON_UHD:chans:undi:18
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  0 undi igr tx 00 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  3 undi igr tx 01 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  4 undi igr tx 02 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  5 undi igr tx 03 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  9 undi igr tx 04 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn  7 undi igr tx 05 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 11 undi igr tx 06 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 15 undi igr tx 07 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 17 undi igr tx 08 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 19 undi igr tx 09 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 25 undi igr tx 10 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 23 undi igr tx 11 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 34 undi igr tx 12 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 36 undi igr tx 13 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 41 undi igr tx 14 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 39 undi igr tx 15 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 29 undi igr tx 16 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_tx_pma lane  2 dev  1 blk 10 chn 37 undi igr tx 17 vod 19 pre1 00 pre2 00 post1 00 post2 00 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  0 undi egr rx 00 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  1 undi egr rx 01 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  3 undi egr rx 02 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  7 undi egr rx 03 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn  6 undi egr rx 04 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 10 undi egr rx 05 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 16 undi egr rx 06 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 15 undi egr rx 07 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 19 undi egr rx 08 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 23 undi egr rx 09 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 22 undi egr rx 10 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 28 undi egr rx 11 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 32 undi egr rx 12 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 34 undi egr rx 13 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 38 undi egr rx 14 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 40 undi egr rx 15 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 31 undi egr rx 16 dc 00 ac 03 vga 04 
set_a10_gxb_rx_pma lane  2 dev  0 blk 10 chn 37 undi egr rx 17 dc 00 ac 03 vga 04 
[201:972935476]setup_board_undi_fpga_xcvr_pma[2] CARBON_UHD: out r=0
[201:972953908]setup_fcb_undi_fpga_xcvr_pma[2] frame_FCB_undi_chans:8
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  0 undi igr tx 00 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  6 undi igr tx 01 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  2 undi igr tx 02 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  6 undi igr tx 03 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  4 undi igr tx 04 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 11 undi igr tx 05 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  8 undi igr tx 06 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  0 undi igr tx 07 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  0 undi egr rx 00 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  6 undi egr rx 01 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  0 undi egr rx 02 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  6 undi egr rx 03 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  4 undi egr rx 04 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 11 undi egr rx 05 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  8 undi egr rx 06 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  2 undi egr rx 07 rx_dc 00 rx_eq 08
[202:136631493]setup_fcb_undi_fpga_xcvr_pma[2] ULTRIX_2NS: out r=0
[202:136668357]setup_board_undi_xpt_chan_pma 2
[202:136686789]setup_board_undi_xpt_chan_pma 2 IGR
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 94 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 2f val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 76 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 27 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 6c val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 1d val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 50 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 5a val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 11 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 62 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 1b val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 6a val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 7 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 5 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page f val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 64 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 21 val 9e r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 30  page 5c val 9e r=0
[202:139414749]setup_board_undi_xpt_chan_pma 2NS LN[2] FCLX RX chan 
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 9 val 59 r=0
[202:139599071]setup_board_undi_xpt_chan_pma 2NS FCLX RX [2] eq1 01 eq0 25 MAP=009
[202:139635935]setup_board_undi_xpt_chan_pma 2 EGR
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 94     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 3d     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 95     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 2f     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 2d     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 4b     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 39     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 88     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 80     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 1b     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 23     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 8d     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 19     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 84     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 7c     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 74     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 86     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 11 td2x_drv 00  page 76     hwval b r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 29     hwval 5 r=0
[202:141460719]setup_board_undi_xpt_chan_pma 2NS FCLX TX [2] sw_drv 05 td2x_drv 00  MAP=003
[202:141516016]CARBON_UHD[2] do_card_boot_pma_init OUT r=0 SUCCESS
rrti_data_test lane 2 dev 1 blk 1  addr 16 sz=496 timeout 250
RRTI BIST PASS: Lane:2 Board:ENDOR_R2 EndDevice:1
FPGA_STATUS:APPLICATION
[02][0][ENDOR_R2]ed01ffff:32000000
[02][1][ENDOR_R2]ed02ffff:42010000
[202:392801659]##############BOARD HW READY
[202:392820091]##############BOARD ONLINE
[202:392856955][2]:CARBON_UHD Starting Monitor Loop
