[57:618005816]MODXIO[3] card_boot_start
FPGA_STATUS:FACTORY
[03][0][HYPERIO]5b30125a:aaaaaa10
[03][1][HYPERIO]5b29123c:aaaaaa10
[57:618190137]##############BOARD HW BOOT
[57:618263866]##############BOARD CALIBRATING
[57:618282298]##############LANE SLOT ENABLE NOT AVAILABLE
[57:618300730]MODXIO[3] START PMA INIT UNDI:18 FCL:6 C2C:0
[57:618319162]MODXIO[3]  UNDI:18 FCL:6 C2C:0
[57:618356027]do_card_boot_pma_init MODXIO[3] set_undi_xcvr_mode
[57:618374459]set_fcb_undi_xcvr_data_mode[3]board_undi_chans:18
[57:618816831]set_fcb_undi_xcvr_data_mode out
[57:618835263]do_card_boot_pma_init MODXIO[3]set_board_undi_xcvr_data_mode 
[57:618872127]set_board_undi_xcvr_data_mode[3] MODXIO:chans:undi:18
[57:618964288]set_board_undi_xcvr_data_mode[3] MODXIO: out r=0
[57:619001152]do_card_boot_pma_init MODXIO[3]set_fcl_igr_mode 
[57:619019584]set_fightclub_igr_eyeq_mode[3] frame FCL chans:16
[57:619480388]set_fightclub_igr_eyeq_mode out
[57:619498821]do_card_boot_pma_init MODXIO[3] set_fcl_egr_mode
[57:619535685]set_fightclub_egr_eyeq_mode[3] BOARD FCL chans:6
[57:619572549]set_fightclub_egr_eyeq_mode out
[57:619590981]set_c2c_eyeq_mode[3]board_c2c_chans:0
[57:619609414]set_c2c_eyeq_mode 54 board->c2c_gxb_map NULL
[57:619627846]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) INGRESS
[57:619646278]setup_board_fcl_fpga_xcvr_pma[3] MODXIO:chans:fcl:6
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 21 fcl igr tx 00 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
[57:619830599]ultrix_2ns_set_fcl_S5_pma_rx [3][0] fcl igr rx 00
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 10 fcl igr rx 00 rx_dc 01 rx_eq 02
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 29 fcl igr tx 02 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
[57:630226338]ultrix_2ns_set_fcl_S5_pma_rx [3][2] fcl igr rx 02
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  9 fcl igr rx 02 rx_dc 01 rx_eq 02
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 31 fcl igr tx 03 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 38 fcl igr tx 04 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
[57:640714237]ultrix_2ns_set_fcl_S5_pma_rx [3][4] fcl igr rx 04
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  8 fcl igr rx 04 rx_dc 02 rx_eq 12
[57:650925654]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) EGRESS 
set_vup_gty_rx_pma lane  3 dev  0 blk 11 chn 21 fcl egr rx 00 rst_wait=:423940(nS) RST_DONE=30c OK: rx_lpmen 01
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 10 fcl egr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_vup_gty_rx_pma lane  3 dev  0 blk 11 chn 29 fcl egr rx 02 rst_wait=:442372(nS) RST_DONE=30c OK: rx_lpmen 01
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  9 fcl egr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_vup_gty_rx_pma lane  3 dev  0 blk 11 chn 31 fcl egr rx 03 rst_wait=:460804(nS) RST_DONE=30c OK: rx_lpmen 01
set_vup_gty_rx_pma lane  3 dev  0 blk 11 chn 38 fcl egr rx 04 rst_wait=:442372(nS) RST_DONE=30c OK: rx_lpmen 01
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  8 fcl egr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[57:683974518]setup_board_fcl_fpga_xcvr_pma[3] MODXIO: out r=0
[57:684011382]setup_board_c2c_fpga_xcvr_pma[3] MODXIO:chans:c2c:6
[57:684029814]setup_board_c2c_fpga_xcvr_pma[3] MODXIO: out r=0
[57:684066679]setup_board_undi_fpga_xcvr_pma[3] MODXIO:chans:undi:18
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 47 undi igr tx 00 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 46 undi igr tx 01 rst_wait=:36864(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 45 undi igr tx 02 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 42 undi igr tx 03 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 41 undi igr tx 04 rst_wait=:18433(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 43 undi igr tx 05 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 39 undi igr tx 06 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 37 undi igr tx 07 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 36 undi igr tx 08 rst_wait=:18433(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 33 undi igr tx 09 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 35 undi igr tx 10 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 32 undi igr tx 11 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 28 undi igr tx 12 rst_wait=:18433(nS) RST_DONE=204 OK diff 12 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 26 undi igr tx 13 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 23 undi igr tx 14 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 22 undi igr tx 15 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 27 undi igr tx 16 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 24 undi igr tx 17 rst_wait=:18433(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 46 undi egr rx 00 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 47 undi egr rx 01 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 45 undi egr rx 02 rst_wait=:36864(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 43 undi egr rx 03 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 42 undi egr rx 04 rst_wait=:36865(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 41 undi egr rx 05 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 39 undi egr rx 06 rst_wait=:36864(nS) RST_DONE=204 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 36 undi egr rx 07 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 37 undi egr rx 08 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 33 undi egr rx 09 rst_wait=:18433(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 35 undi egr rx 10 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 32 undi egr rx 11 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 26 undi egr rx 12 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 27 undi egr rx 13 rst_wait=:36865(nS) RST_DONE=204 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 23 undi egr rx 14 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 22 undi egr rx 15 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 28 undi egr rx 16 rst_wait=:36865(nS) RST_DONE=204 OK diff 12 post 00 pre 00
set_vup_gty_tx_pma lane  3 dev  0 blk 11 chn 24 undi egr rx 17 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
[57:689190819]setup_board_undi_fpga_xcvr_pma[3] MODXIO: out r=0
[57:689227683]setup_fcb_undi_fpga_xcvr_pma[3] frame_FCB_undi_chans:8
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  0 undi igr tx 00 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  6 undi igr tx 01 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  2 undi igr tx 02 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  6 undi igr tx 03 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  4 undi igr tx 04 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 11 undi igr tx 05 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  8 undi igr tx 06 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  0 undi igr tx 07 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  0 undi egr rx 00 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  6 undi egr rx 01 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  0 undi egr rx 02 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  6 undi egr rx 03 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  4 undi egr rx 04 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 11 undi egr rx 05 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  8 undi egr rx 06 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  2 undi egr rx 07 rx_dc 00 rx_eq 08
[57:852536625]setup_fcb_undi_fpga_xcvr_pma[3] ULTRIX_2NS: out r=0
[57:852573489]setup_board_undi_xpt_chan_pma 3
[57:852591921]setup_board_undi_xpt_chan_pma 3 IGR
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 26 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 36 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 37 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 28  page 34 val 9c r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 2c val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 2e val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 2a val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 30 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 32 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 38 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 40 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 3a val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 4a val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 7a val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 8a val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 3b val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 42 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 82 val a0 r=0
[57:855799117]setup_board_undi_xpt_chan_pma 2NS LN[3] FCLX RX chan 
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 2b val 59 r=0
[57:855983439]setup_board_undi_xpt_chan_pma 2NS FCLX RX [3] eq1 01 eq0 25 MAP=043
[57:856001871]setup_board_undi_xpt_chan_pma 3 EGR
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 4f     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 4e     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 96     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 97     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 8e     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 9f     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 65     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 57     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 5f     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 8f     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 87     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 75     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 5c     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 64     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 0d     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 5e     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 56     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 54     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 04 td2x_drv 00  page 27     hwval 4 r=0
[57:857752926]setup_board_undi_xpt_chan_pma 2NS FCLX TX [3] sw_drv 04 td2x_drv 00  MAP=003
[57:857808223]MODXIO[3] do_card_boot_pma_init OUT r=0 SUCCESS
rrtiddr_sb_ddr_init[3][HYPERIO]
SB DDR CALIB[3] BANK[0] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[3] BANK[0] DONE ret=(0) PASS
SB DDR CALIB[3] BANK[1] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[3] BANK[1] DONE ret=(0) PASS
SB DDR CALIB[3] BANK[2] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[3] BANK[2] DONE ret=(0) PASS
SB DDR CALIB[3] BANK[3] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[3] BANK[3] DONE ret=(0) PASS
rrti_data_test lane 3 dev 1 blk 1  addr 16 sz=496 timeout 250
RRTI BIST PASS: Lane:3 Board:HYPERIO EndDevice:1
FPGA_STATUS:APPLICATION
[03][0][HYPERIO]5b30125a:aaaaaa10
[03][1][HYPERIO]5b29123c:aaaaaa10
[59:905971458]##############BOARD HW READY
[59:906008322]##############BOARD ONLINE
[59:906026754][3]:MODXIO Starting Monitor Loop
