[18:620272977]HD_IOBNC[1] card_boot_start
FPGA_STATUS:FACTORY
[01][0][IOBNC]10b105df:fac7ff11
[01][1][IOBNC]10b205df:fac7ff11
[01][2][IOBNC]10b205df:fac7ff11
[18:620531027]##############BOARD HW BOOT
[18:620733781]HD_IOBNC[1] BOOT ALL FPGAS NUM_FPGAS=3 FAC_ADDR=0 APP_ADDR=1080000
[18:620770645]HD_IOBNC[1][2] BOOT TRY 0
[18:620789077]card_boot_fpga HD_IOBNC[1][2] BOOT START
[18:620881238]card_boot_fpga HD_IOBNC[1][2] Starting with ID[10b205df]:VER[fac7ff11]
[18:620899670]card_boot_fpga HD_IOBNC[1][2] OLD FAC :VER[1503]
[18:620936535]card_boot_fpga HD_IOBNC[1][2] Loading Factory Bitfile ADDR[00000000]
[18:621010263]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[2]BLK:[2] ADDR=0
[18:705945659]card_boot_fpga HD_IOBNC[1][2] FACTORY IMAGE RECONFIG: SUCCESS
[18:706000955]card_boot_fpga HD_IOBNC[1][2] FACTORY_RRTI_UP:1 TIME:0:00018 
[18:706056252]card_boot_fpga HD_IOBNC[1][2] FACTORY_RECONFIG_OK:1 TIME:0:84972
[18:706093116]card_boot_fpga HD_IOBNC[1][2] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[18:706111548]card_boot_fpga HD_IOBNC[1][2] Loading Application Bitfile ADDR[1080000]
[19:906671886]OLD FACTORY BOOT MODE
[19:973893975]card_boot_fpga HD_IOBNC[1][2] APP IMAGE RECONFIG: SUCCESS
[19:973949271]card_boot_fpga HD_IOBNC[1][2] APP_RRTI_UP:1 TIME:0:00018 
[19:973986136]card_boot_fpga HD_IOBNC[1][2] APP_RECONFIG_OK:1 TIME:1:267745
[19:974023000]card_boot_fpga HD_IOBNC[1][2] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[19:974059864]HD_IOBNC[1][2] BOOT OK in 1:353289219

[19:974096728]HD_IOBNC[1][1] BOOT TRY 0
[19:974115161]card_boot_fpga HD_IOBNC[1][1] BOOT START
[19:974207321]card_boot_fpga HD_IOBNC[1][1] Starting with ID[10b205df]:VER[fac7ff11]
[19:974244186]card_boot_fpga HD_IOBNC[1][1] OLD FAC :VER[1503]
[19:974262618]card_boot_fpga HD_IOBNC[1][1] Loading Factory Bitfile ADDR[00000000]
[19:974317914]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[1]BLK:[2] ADDR=0
[20:47825370]card_boot_fpga HD_IOBNC[1][1] FACTORY IMAGE RECONFIG: SUCCESS
[20:47880667]card_boot_fpga HD_IOBNC[1][1] FACTORY_RRTI_UP:1 TIME:0:00073 
[20:47935963]card_boot_fpga HD_IOBNC[1][1] FACTORY_RECONFIG_OK:1 TIME:0:73525
[20:47954395]card_boot_fpga HD_IOBNC[1][1] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[20:47991260]card_boot_fpga HD_IOBNC[1][1] Loading Application Bitfile ADDR[1080000]
[21:248459436]OLD FACTORY BOOT MODE
[21:309506752]card_boot_fpga HD_IOBNC[1][1] APP IMAGE RECONFIG: SUCCESS
[21:309617345]card_boot_fpga HD_IOBNC[1][1] APP_RRTI_UP:1 TIME:0:00018 
[21:309654209]card_boot_fpga HD_IOBNC[1][1] APP_RECONFIG_OK:1 TIME:1:261478
[21:309691073]card_boot_fpga HD_IOBNC[1][1] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[21:309727938]HD_IOBNC[1][1] BOOT OK in 1:335631210

[21:309746370]HD_IOBNC[1][0] BOOT TRY 0
[21:309783234]card_boot_fpga HD_IOBNC[1][0] BOOT START
[21:309838531]card_boot_fpga HD_IOBNC[1][0] Starting with ID[10b105df]:VER[fac7ff11]
[21:309875395]card_boot_fpga HD_IOBNC[1][0] OLD FAC :VER[1503]
[21:309912259]card_boot_fpga HD_IOBNC[1][0] Loading Factory Bitfile ADDR[00000000]
[21:309967556]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[0]BLK:[2] ADDR=0
[21:375254268]card_boot_fpga HD_IOBNC[1][0] FACTORY IMAGE RECONFIG: SUCCESS
[21:375327997]card_boot_fpga HD_IOBNC[1][0] FACTORY_RRTI_UP:1 TIME:0:00018 
[21:375364861]card_boot_fpga HD_IOBNC[1][0] FACTORY_RECONFIG_OK:1 TIME:0:65305
[21:375383293]card_boot_fpga HD_IOBNC[1][0] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[21:375420157]card_boot_fpga HD_IOBNC[1][0] Loading Application Bitfile ADDR[1080000]
[22:575888334]OLD FACTORY BOOT MODE
[22:643239448]card_boot_fpga HD_IOBNC[1][0] APP IMAGE RECONFIG: SUCCESS
[22:643368473]card_boot_fpga HD_IOBNC[1][0] APP_RRTI_UP:1 TIME:0:00018 
[22:643405338]card_boot_fpga HD_IOBNC[1][0] APP_RECONFIG_OK:1 TIME:1:267782
[22:643442202]card_boot_fpga HD_IOBNC[1][0] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[22:643479066]HD_IOBNC[1][0] BOOT OK in 1:333732696

[22:689799086]HD_IOBNC[1] HOST_RESET SUCCESS TRY=1 r=0
[22:689854382]HD_IOBNC[1] BOOTED ALL 3 FPGAS OK took 4:333732696
[22:689983407]##############BOARD CALIBRATING
[22:690038704]##############LANE SLOT ENABLE NOT AVAILABLE
[22:690075568]HD_IOBNC[1] START PMA INIT UNDI:18 FCL:6 C2C:6
[22:690112432]HD_IOBNC[1]  UNDI:18 FCL:6 C2C:6
[22:690149297]do_card_boot_pma_init HD_IOBNC[1] set_undi_xcvr_mode
[22:690167729]set_fcb_undi_xcvr_data_mode[1]board_undi_chans:18
[22:691273658]set_fcb_undi_xcvr_data_mode out
[22:691310523]do_card_boot_pma_init HD_IOBNC[1]set_board_undi_xcvr_data_mode 
[22:691328955]set_board_undi_xcvr_data_mode[1] HD_IOBNC:chans:undi:18
[22:692434885]set_board_undi_xcvr_data_mode[1] HD_IOBNC: out r=0
[22:692471749]do_card_boot_pma_init HD_IOBNC[1]set_fcl_igr_mode 
[22:692490181]set_fightclub_igr_eyeq_mode[1] frame FCL chans:16
[22:692969417]set_fightclub_igr_eyeq_mode out
[22:692987849]do_card_boot_pma_init HD_IOBNC[1] set_fcl_egr_mode
[22:693024714]set_fightclub_egr_eyeq_mode[1] BOARD FCL chans:6
[22:693245900]set_fightclub_egr_eyeq_mode out
[22:693282764]set_c2c_eyeq_mode[1]board_c2c_chans:6
[22:693632975]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) INGRESS
[22:693651407]setup_board_fcl_fpga_xcvr_pma[1] HD_IOBNC:chans:fcl:6
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 20 fcl igr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[22:703954985]ultrix_2ns_set_fcl_S5_pma_rx [1][0] fcl igr rx 00
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn 11 fcl igr rx 00 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 20 fcl igr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[22:724469979]ultrix_2ns_set_fcl_S5_pma_rx [1][2] fcl igr rx 02
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn 10 fcl igr rx 02 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 22 fcl igr tx 03 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 20 fcl igr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[22:755436009]ultrix_2ns_set_fcl_S5_pma_rx [1][4] fcl igr rx 04
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  9 fcl igr rx 04 rx_dc 01 rx_eq 08
[22:765665858]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) EGRESS 
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  6 fcl egr rx 00 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn 11 fcl egr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  6 fcl egr rx 02 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn 10 fcl egr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  7 fcl egr rx 03 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  6 fcl egr rx 04 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  9 fcl egr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[22:837237937]setup_board_fcl_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[22:837256369]setup_board_c2c_fpga_xcvr_pma[1] HD_IOBNC:chans:c2c:6
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 22 c2c tx 00 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  6 c2c rx 00 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 24 c2c tx 01 tx_vod 40 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  7 c2c rx 01 rx_dc 00 rx_eq 06
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 22 c2c tx 02 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  6 c2c rx 02 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 24 c2c tx 03 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  7 c2c rx 03 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 22 c2c tx 04 tx_vod 40 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  6 c2c rx 04 rx_dc 00 rx_eq 06
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 24 c2c tx 05 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  7 c2c rx 05 rx_dc 00 rx_eq 02
[22:960254176]setup_board_c2c_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[22:960272608]setup_board_undi_fpga_xcvr_pma[1] HD_IOBNC:chans:undi:18
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 12 undi igr tx 00 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 18 undi igr tx 01 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 14 undi igr tx 02 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 16 undi igr tx 03 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 18 undi igr tx 04 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 20 undi igr tx 05 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 12 undi igr tx 06 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 18 undi igr tx 07 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 14 undi igr tx 08 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 16 undi igr tx 09 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 18 undi igr tx 10 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 20 undi igr tx 11 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 18 undi igr tx 12 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 12 undi igr tx 13 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 14 undi igr tx 14 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 20 undi igr tx 15 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 16 undi igr tx 16 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 18 undi igr tx 17 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  2 undi egr rx 00 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  4 undi egr rx 01 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  3 undi egr rx 02 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  4 undi egr rx 03 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  5 undi egr rx 04 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  5 undi egr rx 05 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  2 undi egr rx 06 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  4 undi egr rx 07 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  3 undi egr rx 08 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  4 undi egr rx 09 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  5 undi egr rx 10 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  5 undi egr rx 11 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  2 undi egr rx 12 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  3 undi egr rx 13 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  4 undi egr rx 14 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  5 undi egr rx 15 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  4 undi egr rx 16 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  5 undi egr rx 17 rx_dc 00 rx_eq 03
[23:328749927]setup_board_undi_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[23:328786791]setup_fcb_undi_fpga_xcvr_pma[1] frame_FCB_undi_chans:8
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  0 undi igr tx 00 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  6 undi igr tx 01 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  2 undi igr tx 02 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  6 undi igr tx 03 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  4 undi igr tx 04 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 11 undi igr tx 05 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  8 undi igr tx 06 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  0 undi igr tx 07 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  0 undi egr rx 00 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  6 undi egr rx 01 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  0 undi egr rx 02 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  6 undi egr rx 03 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  4 undi egr rx 04 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 11 undi egr rx 05 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  8 undi egr rx 06 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  2 undi egr rx 07 rx_dc 00 rx_eq 08
[23:491598064]setup_fcb_undi_fpga_xcvr_pma[1] ULTRIX_2NS: out r=0
[23:491634929]setup_board_undi_xpt_chan_pma 1
[23:491653361]setup_board_undi_xpt_chan_pma 1 IGR
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1e val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1c val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 16 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 17 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page e val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 14 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page d val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 6 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 0 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 2 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 3 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 10 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 23 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1a val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 22 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 12 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 18 val 59 r=0
[23:494455049]setup_board_undi_xpt_chan_pma 2NS LN[1] FCLX RX chan 
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page c val 59 r=0
[23:494639371]setup_board_undi_xpt_chan_pma 2NS FCLX RX [1] eq1 01 eq0 25 MAP=012
[23:494676235]setup_board_undi_xpt_chan_pma 1 EGR
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 42     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 48     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 41     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 38     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3a     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 32     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 9a     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 49     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 43     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 18     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3b     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 12     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 01     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 52     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 09     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 11     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 00     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 62     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 90     hwval 5 r=0
[23:496427290]setup_board_undi_xpt_chan_pma 2NS FCLX TX [1] sw_drv 05 td2x_drv 00  MAP=003
[23:496482587]HD_IOBNC[1] do_card_boot_pma_init OUT r=0 SUCCESS
rrtiddr_iobnc_ddr_init[1] IN
DDR CALIBRATE[1][0] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][0] DONE ret=(0) PASS
DDR CALIBRATE[1][1] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][1] DONE ret=(0) PASS
DDR CALIBRATE[1][2] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][2] DONE ret=(0) PASS
rrti_data_test lane 1 dev 2 blk 1  addr 16 sz=496 timeout 250
RRTI BIST PASS: Lane:1 Board:IOBNC EndDevice:2
FPGA_STATUS:APPLICATION
[01][0][IOBNC]10b1125a:aaaaaa10
[01][1][IOBNC]10b2125a:aaaaaa10
[01][2][IOBNC]10b2125a:aaaaaa10
[24:223078351]##############BOARD HW READY
[24:223096783]##############BOARD ONLINE
[24:223133648][1]:HD_IOBNC Starting Monitor Loop
