[29:16269510]HD_IOBNC[1] card_boot_start
FPGA_STATUS:FACTORY
[01][0][IOBNC]10b105df:fac7ff11
[01][1][IOBNC]10b205df:fac7ff11
[01][2][IOBNC]10b205df:fac7ff11
[29:16490696]##############BOARD HW BOOT
[29:16619721]HD_IOBNC[1] BOOT ALL FPGAS NUM_FPGAS=3 FAC_ADDR=0 APP_ADDR=1080000
[29:16656585]HD_IOBNC[1][2] BOOT TRY 0
[29:16675018]card_boot_fpga HD_IOBNC[1][2] BOOT START
[29:16748746]card_boot_fpga HD_IOBNC[1][2] Starting with ID[10b205df]:VER[fac7ff11]
[29:16785611]card_boot_fpga HD_IOBNC[1][2] OLD FAC :VER[1503]
[29:16822475]card_boot_fpga HD_IOBNC[1][2] Loading Factory Bitfile ADDR[00000000]
[29:16877771]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[2]BLK:[2] ADDR=0
[29:102587317]card_boot_fpga HD_IOBNC[1][2] FACTORY IMAGE RECONFIG: SUCCESS
[29:102642614]card_boot_fpga HD_IOBNC[1][2] FACTORY_RRTI_UP:1 TIME:0:00036 
[29:102679478]card_boot_fpga HD_IOBNC[1][2] FACTORY_RECONFIG_OK:1 TIME:0:85746
[29:102734775]card_boot_fpga HD_IOBNC[1][2] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[29:102753207]card_boot_fpga HD_IOBNC[1][2] Loading Application Bitfile ADDR[1080000]
[30:305838750]OLD FACTORY BOOT MODE
[30:389870970]card_boot_fpga HD_IOBNC[1][2] APP IMAGE RECONFIG: SUCCESS
[30:389926266]card_boot_fpga HD_IOBNC[1][2] APP_RRTI_UP:1 TIME:0:00018 
[30:389963131]card_boot_fpga HD_IOBNC[1][2] APP_RECONFIG_OK:1 TIME:1:287080
[30:390036859]card_boot_fpga HD_IOBNC[1][2] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[30:390092156]HD_IOBNC[1][2] BOOT OK in 1:373435571

[30:390147452]HD_IOBNC[1][1] BOOT TRY 0
[30:390202749]card_boot_fpga HD_IOBNC[1][1] BOOT START
[30:390350206]card_boot_fpga HD_IOBNC[1][1] Starting with ID[10b205df]:VER[fac7ff11]
[30:390423935]card_boot_fpga HD_IOBNC[1][1] OLD FAC :VER[1503]
[30:390479231]card_boot_fpga HD_IOBNC[1][1] Loading Factory Bitfile ADDR[00000000]
[30:390589824]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[1]BLK:[2] ADDR=0
[30:479395973]card_boot_fpga HD_IOBNC[1][1] FACTORY IMAGE RECONFIG: SUCCESS
[30:479451269]card_boot_fpga HD_IOBNC[1][1] FACTORY_RRTI_UP:1 TIME:0:00110 
[30:479488134]card_boot_fpga HD_IOBNC[1][1] FACTORY_RECONFIG_OK:1 TIME:0:88824
[30:479524998]card_boot_fpga HD_IOBNC[1][1] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[30:479543430]card_boot_fpga HD_IOBNC[1][1] Loading Application Bitfile ADDR[1080000]
[31:680011607]OLD FACTORY BOOT MODE
[31:738828631]card_boot_fpga HD_IOBNC[1][1] APP IMAGE RECONFIG: SUCCESS
[31:738883927]card_boot_fpga HD_IOBNC[1][1] APP_RRTI_UP:1 TIME:0:00018 
[31:738920792]card_boot_fpga HD_IOBNC[1][1] APP_RECONFIG_OK:1 TIME:1:259248
[31:738957656]card_boot_fpga HD_IOBNC[1][1] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[31:738994520]HD_IOBNC[1][1] BOOT OK in 1:348847068

[31:739012952]HD_IOBNC[1][0] BOOT TRY 0
[31:739049817]card_boot_fpga HD_IOBNC[1][0] BOOT START
[31:739105113]card_boot_fpga HD_IOBNC[1][0] Starting with ID[10b105df]:VER[fac7ff11]
[31:739141978]card_boot_fpga HD_IOBNC[1][0] OLD FAC :VER[1503]
[31:739178842]card_boot_fpga HD_IOBNC[1][0] Loading Factory Bitfile ADDR[00000000]
[31:739215706]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[0]BLK:[2] ADDR=0
[31:805276569]card_boot_fpga HD_IOBNC[1][0] FACTORY IMAGE RECONFIG: SUCCESS
[31:805350298]card_boot_fpga HD_IOBNC[1][0] FACTORY_RRTI_UP:1 TIME:0:00018 
[31:805387162]card_boot_fpga HD_IOBNC[1][0] FACTORY_RECONFIG_OK:1 TIME:0:66060
[31:805442459]card_boot_fpga HD_IOBNC[1][0] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[31:805479323]card_boot_fpga HD_IOBNC[1][0] Loading Application Bitfile ADDR[1080000]
[33:6076525]OLD FACTORY BOOT MODE
[33:73151157]card_boot_fpga HD_IOBNC[1][0] APP IMAGE RECONFIG: SUCCESS
[33:73206453]card_boot_fpga HD_IOBNC[1][0] APP_RRTI_UP:1 TIME:0:00018 
[33:73243317]card_boot_fpga HD_IOBNC[1][0] APP_RECONFIG_OK:1 TIME:1:267616
[33:73280182]card_boot_fpga HD_IOBNC[1][0] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[33:73317046]HD_IOBNC[1][0] BOOT OK in 1:334304094

[33:119766090]HD_IOBNC[1] HOST_RESET SUCCESS TRY=1 r=0
[33:119821387]HD_IOBNC[1] BOOTED ALL 3 FPGAS OK took 4:334304094
[33:119931980]##############BOARD CALIBRATING
[33:119950412]##############LANE SLOT ENABLE NOT AVAILABLE
[33:119968844]HD_IOBNC[1] START PMA INIT UNDI:18 FCL:6 C2C:6
[33:120024141]HD_IOBNC[1]  UNDI:18 FCL:6 C2C:6
[33:120097869]do_card_boot_pma_init HD_IOBNC[1] set_undi_xcvr_mode
[33:120190030]set_fcb_undi_xcvr_data_mode[1]board_undi_chans:18
[33:120908884]set_fcb_undi_xcvr_data_mode out
[33:120964181]do_card_boot_pma_init HD_IOBNC[1]set_board_undi_xcvr_data_mode 
[33:121001045]set_board_undi_xcvr_data_mode[1] HD_IOBNC:chans:undi:18
[33:122014814]set_board_undi_xcvr_data_mode[1] HD_IOBNC: out r=0
[33:122051678]do_card_boot_pma_init HD_IOBNC[1]set_fcl_igr_mode 
[33:122088543]set_fightclub_igr_eyeq_mode[1] frame FCL chans:16
[33:122512482]set_fightclub_igr_eyeq_mode out
[33:122530914]do_card_boot_pma_init HD_IOBNC[1] set_fcl_egr_mode
[33:122567779]set_fightclub_egr_eyeq_mode[1] BOARD FCL chans:6
[33:122752100]set_fightclub_egr_eyeq_mode out
[33:122770533]set_c2c_eyeq_mode[1]board_c2c_chans:6
[33:123139176]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) INGRESS
[33:123157608]setup_board_fcl_fpga_xcvr_pma[1] HD_IOBNC:chans:fcl:6
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 20 fcl igr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:133387457]ultrix_2ns_set_fcl_S5_pma_rx [1][0] fcl igr rx 00
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn 11 fcl igr rx 00 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 20 fcl igr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:153754994]ultrix_2ns_set_fcl_S5_pma_rx [1][2] fcl igr rx 02
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn 10 fcl igr rx 02 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 22 fcl igr tx 03 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 20 fcl igr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:184536702]ultrix_2ns_set_fcl_S5_pma_rx [1][4] fcl igr rx 04
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  9 fcl igr rx 04 rx_dc 01 rx_eq 08
[33:194766551]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) EGRESS 
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  6 fcl egr rx 00 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn 11 fcl egr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  6 fcl egr rx 02 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn 10 fcl egr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  7 fcl egr rx 03 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  6 fcl egr rx 04 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  9 fcl egr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:266725705]setup_board_fcl_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[33:266744138]setup_board_c2c_fpga_xcvr_pma[1] HD_IOBNC:chans:c2c:6
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 22 c2c tx 00 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  6 c2c rx 00 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 24 c2c tx 01 tx_vod 40 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  7 c2c rx 01 rx_dc 00 rx_eq 06
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 22 c2c tx 02 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  6 c2c rx 02 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 24 c2c tx 03 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  7 c2c rx 03 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 22 c2c tx 04 tx_vod 40 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  6 c2c rx 04 rx_dc 00 rx_eq 06
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 24 c2c tx 05 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  7 c2c rx 05 rx_dc 00 rx_eq 02
[33:388967793]setup_board_c2c_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[33:389004658]setup_board_undi_fpga_xcvr_pma[1] HD_IOBNC:chans:undi:18
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 12 undi igr tx 00 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 18 undi igr tx 01 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 14 undi igr tx 02 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 16 undi igr tx 03 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 18 undi igr tx 04 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 20 undi igr tx 05 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 12 undi igr tx 06 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 18 undi igr tx 07 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 14 undi igr tx 08 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 16 undi igr tx 09 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 18 undi igr tx 10 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 20 undi igr tx 11 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 18 undi igr tx 12 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 12 undi igr tx 13 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 14 undi igr tx 14 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 20 undi igr tx 15 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 16 undi igr tx 16 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 18 undi igr tx 17 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  2 undi egr rx 00 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  4 undi egr rx 01 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  3 undi egr rx 02 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  4 undi egr rx 03 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  5 undi egr rx 04 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  5 undi egr rx 05 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  2 undi egr rx 06 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  4 undi egr rx 07 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  3 undi egr rx 08 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  4 undi egr rx 09 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  5 undi egr rx 10 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  5 undi egr rx 11 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  2 undi egr rx 12 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  3 undi egr rx 13 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  4 undi egr rx 14 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  5 undi egr rx 15 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  4 undi egr rx 16 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  5 undi egr rx 17 rx_dc 00 rx_eq 03
[33:755583464]setup_board_undi_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[33:755620329]setup_fcb_undi_fpga_xcvr_pma[1] frame_FCB_undi_chans:8
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  0 undi igr tx 00 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  6 undi igr tx 01 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  2 undi igr tx 02 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  6 undi igr tx 03 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  4 undi igr tx 04 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 11 undi igr tx 05 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  8 undi igr tx 06 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  0 undi igr tx 07 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  0 undi egr rx 00 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  6 undi egr rx 01 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  0 undi egr rx 02 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  6 undi egr rx 03 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  4 undi egr rx 04 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 11 undi egr rx 05 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  8 undi egr rx 06 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  2 undi egr rx 07 rx_dc 00 rx_eq 08
[33:918468466]setup_fcb_undi_fpga_xcvr_pma[1] ULTRIX_2NS: out r=0
[33:918505330]setup_board_undi_xpt_chan_pma 1
[33:918542195]setup_board_undi_xpt_chan_pma 1 IGR
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1e val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1c val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 16 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 17 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page e val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 14 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page d val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 6 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 0 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 2 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 3 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 10 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 23 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1a val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 22 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 12 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 18 val 59 r=0
[33:921343883]setup_board_undi_xpt_chan_pma 2NS LN[1] FCLX RX chan 
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page c val 59 r=0
[33:921546637]setup_board_undi_xpt_chan_pma 2NS FCLX RX [1] eq1 01 eq0 25 MAP=012
[33:921565069]setup_board_undi_xpt_chan_pma 1 EGR
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 42     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 48     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 41     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 38     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3a     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 32     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 9a     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 49     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 43     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 18     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3b     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 12     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 01     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 52     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 09     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 11     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 00     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 62     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 90     hwval 5 r=0
[33:923389853]setup_board_undi_xpt_chan_pma 2NS FCLX TX [1] sw_drv 05 td2x_drv 00  MAP=003
[33:923445149]HD_IOBNC[1] do_card_boot_pma_init OUT r=0 SUCCESS
rrtiddr_iobnc_ddr_init[1] IN
DDR CALIBRATE[1][0] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][0] DONE ret=(0) PASS
DDR CALIBRATE[1][1] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][1] DONE ret=(0) PASS
DDR CALIBRATE[1][2] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][2] DONE ret=(0) PASS
rrti_data_test lane 1 dev 2 blk 1  addr 16 sz=496 timeout 250
RRTI BIST PASS: Lane:1 Board:IOBNC EndDevice:2
FPGA_STATUS:APPLICATION
[01][0][IOBNC]10b1125a:aaaaaa10
[01][1][IOBNC]10b2125a:aaaaaa10
[01][2][IOBNC]10b2125a:aaaaaa10
[34:652879466]##############BOARD HW READY
[34:652916331]##############BOARD ONLINE
[34:652934763][1]:HD_IOBNC Starting Monitor Loop
