[58:836242595]HDXIO[4] card_boot_start
FPGA_STATUS:FACTORY
[04][0][SBSDI]5b5d125a:aaaaaa10
[04][1][SBSDI]5b29123c:aaaaaa10
[58:836426917]##############BOARD HW BOOT
[58:836500645]##############BOARD CALIBRATING
[58:836519077]##############LANE SLOT ENABLE NOT AVAILABLE
[58:836537509]HDXIO[4] START PMA INIT UNDI:18 FCL:6 C2C:0
[58:836574374]HDXIO[4]  UNDI:18 FCL:6 C2C:0
[58:836592806]do_card_boot_pma_init HDXIO[4] set_undi_xcvr_mode
[58:836611238]set_fcb_undi_xcvr_data_mode[4]board_undi_chans:18
[58:837053610]set_fcb_undi_xcvr_data_mode out
[58:837072042]do_card_boot_pma_init HDXIO[4]set_board_undi_xcvr_data_mode 
[58:837108906]set_board_undi_xcvr_data_mode[4] HDXIO:chans:undi:18
[58:837182635]set_board_undi_xcvr_data_mode[4] HDXIO: out r=0
[58:837201067]do_card_boot_pma_init HDXIO[4]set_fcl_igr_mode 
[58:837237932]set_fightclub_igr_eyeq_mode[4] frame FCL chans:16
[58:837661871]set_fightclub_igr_eyeq_mode out
[58:837698736]do_card_boot_pma_init HDXIO[4] set_fcl_egr_mode
[58:837717168]set_fightclub_egr_eyeq_mode[4] BOARD FCL chans:6
[58:837754032]set_fightclub_egr_eyeq_mode out
[58:837772464]set_c2c_eyeq_mode[4]board_c2c_chans:0
[58:837790896]set_c2c_eyeq_mode 54 board->c2c_gxb_map NULL
[58:837809329]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) INGRESS
[58:837827761]setup_board_fcl_fpga_xcvr_pma[4] HDXIO:chans:fcl:6
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 21 fcl igr tx 00 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
[58:838012082]ultrix_2ns_set_fcl_S5_pma_rx [4][0] fcl igr rx 00
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  5 fcl igr rx 00 rx_dc 01 rx_eq 02
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 29 fcl igr tx 02 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
[58:848370956]ultrix_2ns_set_fcl_S5_pma_rx [4][2] fcl igr rx 02
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  3 fcl igr rx 02 rx_dc 01 rx_eq 02
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 31 fcl igr tx 03 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 38 fcl igr tx 04 rst_wait=:18432(nS) RST_DONE=304 OK diff 16 post 00 pre 00
[58:858877288]ultrix_2ns_set_fcl_S5_pma_rx [4][4] fcl igr rx 04
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  2 fcl igr rx 04 rx_dc 02 rx_eq 12
[58:869070273]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) EGRESS 
set_vup_gty_rx_pma lane  4 dev  0 blk 11 chn 21 fcl egr rx 00 rst_wait=:442372(nS) RST_DONE=30c OK: rx_lpmen 01
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  5 fcl egr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_vup_gty_rx_pma lane  4 dev  0 blk 11 chn 29 fcl egr rx 02 rst_wait=:442371(nS) RST_DONE=30c OK: rx_lpmen 01
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  3 fcl egr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_vup_gty_rx_pma lane  4 dev  0 blk 11 chn 31 fcl egr rx 03 rst_wait=:442372(nS) RST_DONE=30c OK: rx_lpmen 01
set_vup_gty_rx_pma lane  4 dev  0 blk 11 chn 38 fcl egr rx 04 rst_wait=:442372(nS) RST_DONE=30c OK: rx_lpmen 01
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  2 fcl egr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[58:901916383]setup_board_fcl_fpga_xcvr_pma[4] HDXIO: out r=0
[58:901953247]setup_board_c2c_fpga_xcvr_pma[4] HDXIO:chans:c2c:6
[58:901971679]setup_board_c2c_fpga_xcvr_pma[4] HDXIO: out r=0
[58:902008543]setup_board_undi_fpga_xcvr_pma[4] HDXIO:chans:undi:18
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 47 undi igr tx 00 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 46 undi igr tx 01 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 45 undi igr tx 02 rst_wait=:36864(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 42 undi igr tx 03 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 41 undi igr tx 04 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 43 undi igr tx 05 rst_wait=:18433(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 39 undi igr tx 06 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 37 undi igr tx 07 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 36 undi igr tx 08 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 33 undi igr tx 09 rst_wait=:18433(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 35 undi igr tx 10 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 32 undi igr tx 11 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 28 undi igr tx 12 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 26 undi igr tx 13 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 23 undi igr tx 14 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 22 undi igr tx 15 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 27 undi igr tx 16 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 24 undi igr tx 17 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 46 undi egr rx 00 rst_wait=:18433(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 47 undi egr rx 01 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 45 undi egr rx 02 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 43 undi egr rx 03 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 06
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 42 undi egr rx 04 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 00
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 41 undi egr rx 05 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 39 undi egr rx 06 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 36 undi egr rx 07 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 37 undi egr rx 08 rst_wait=:18432(nS) RST_DONE=204 OK diff 16 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 33 undi egr rx 09 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 35 undi egr rx 10 rst_wait=:18433(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 32 undi egr rx 11 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 26 undi egr rx 12 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 27 undi egr rx 13 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 23 undi egr rx 14 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 22 undi egr rx 15 rst_wait=:36864(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 28 undi egr rx 16 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
set_vup_gty_tx_pma lane  4 dev  0 blk 11 chn 24 undi egr rx 17 rst_wait=:18432(nS) RST_DONE=204 OK diff 12 post 00 pre 12
[58:907151116]setup_board_undi_fpga_xcvr_pma[4] HDXIO: out r=0
[58:907169548]setup_fcb_undi_fpga_xcvr_pma[4] frame_FCB_undi_chans:8
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  0 undi igr tx 00 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  6 undi igr tx 01 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  2 undi igr tx 02 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  6 undi igr tx 03 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  4 undi igr tx 04 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 11 undi igr tx 05 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  8 undi igr tx 06 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  0 undi igr tx 07 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  0 undi egr rx 00 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  6 undi egr rx 01 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  0 undi egr rx 02 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  6 undi egr rx 03 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  4 undi egr rx 04 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 11 undi egr rx 05 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  8 undi egr rx 06 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  2 undi egr rx 07 rx_dc 00 rx_eq 08
[59:70091414]setup_fcb_undi_fpga_xcvr_pma[4] ULTRIX_2NS: out r=0
[59:70128279]setup_board_undi_xpt_chan_pma 4
[59:70146711]setup_board_undi_xpt_chan_pma 4 IGR
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 44 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 4c val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 46 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 47 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 4f val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 4e val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 99 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 98 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 9a val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 28  page 93 val 9c r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 90 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 83 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 88 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 80 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 49 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 78 val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 7b val a0 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 02 eq0 32  page 4b val a0 r=0
[59:72929967]setup_board_undi_xpt_chan_pma 2NS LN[4] FCLX RX chan 
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 9b val 59 r=0
[59:73114289]setup_board_undi_xpt_chan_pma 2NS FCLX RX [4] eq1 01 eq0 25 MAP=155
[59:73151153]setup_board_undi_xpt_chan_pma 4 EGR
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 36     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 34     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3c     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 47     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 8c     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 46     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 0e     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 0c     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 0f     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 1c     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 16     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 1d     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 1e     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 24     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 1f     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 25     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 05     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 6e     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 14     hwval 5 r=0
[59:74902208]setup_board_undi_xpt_chan_pma 2NS FCLX TX [4] sw_drv 05 td2x_drv 00  MAP=003
[59:74957505]HDXIO[4] do_card_boot_pma_init OUT r=0 SUCCESS
rrtiddr_sb_ddr_init[4][SBSDI]
SB DDR CALIB[4] BANK[0] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[4] BANK[0] DONE ret=(0) PASS
SB DDR CALIB[4] BANK[1] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[4] BANK[1] DONE ret=(0) PASS
SB DDR CALIB[4] BANK[2] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[4] BANK[2] DONE ret=(0) PASS
SB DDR CALIB[4] BANK[3] DONE ret=(0)
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
SB DDR AUDIO[4] BANK[3] DONE ret=(0) PASS
rrti_data_test lane 4 dev 1 blk 1  addr 16 sz=496 timeout 250
RRTI BIST PASS: Lane:4 Board:SBSDI EndDevice:1
FPGA_STATUS:APPLICATION
[04][0][SBSDI]5b5d125a:aaaaaa10
[04][1][SBSDI]5b29123c:aaaaaa10
[62:126198910]##############BOARD HW READY
[62:126235775]##############BOARD ONLINE
[62:126254207][4]:HDXIO Starting Monitor Loop
