[29:113904664]HD_IOBNC[1] card_boot_start
FPGA_STATUS:FACTORY
[01][0][IOBNC]10b105df:fac7ff11
[01][1][IOBNC]10b205df:fac7ff11
[01][2][IOBNC]10b205df:fac7ff11
[29:114291739]##############BOARD HW BOOT
[29:114347036]HD_IOBNC[1] BOOT ALL FPGAS NUM_FPGAS=3 FAC_ADDR=0 APP_ADDR=1080000
[29:114383900]HD_IOBNC[1][2] BOOT TRY 0
[29:114439197]card_boot_fpga HD_IOBNC[1][2] BOOT START
[29:114549790]card_boot_fpga HD_IOBNC[1][2] Starting with ID[10b205df]:VER[fac7ff11]
[29:114641950]card_boot_fpga HD_IOBNC[1][2] OLD FAC :VER[1503]
[29:114715679]card_boot_fpga HD_IOBNC[1][2] Loading Factory Bitfile ADDR[00000000]
[29:114826272]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[2]BLK:[2] ADDR=0
[29:200757004]card_boot_fpga HD_IOBNC[1][2] FACTORY IMAGE RECONFIG: SUCCESS
[29:200812300]card_boot_fpga HD_IOBNC[1][2] FACTORY_RRTI_UP:1 TIME:0:00258 
[29:200849165]card_boot_fpga HD_IOBNC[1][2] FACTORY_RECONFIG_OK:1 TIME:0:86004
[29:200886029]card_boot_fpga HD_IOBNC[1][2] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[29:200922893]card_boot_fpga HD_IOBNC[1][2] Loading Application Bitfile ADDR[1080000]
[30:410164778]OLD FACTORY BOOT MODE
[30:470603832]card_boot_fpga HD_IOBNC[1][2] APP IMAGE RECONFIG: SUCCESS
[30:470659129]card_boot_fpga HD_IOBNC[1][2] APP_RRTI_UP:1 TIME:0:00036 
[30:470695993]card_boot_fpga HD_IOBNC[1][2] APP_RECONFIG_OK:1 TIME:1:269644
[30:470732858]card_boot_fpga HD_IOBNC[1][2] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[30:470769722]HD_IOBNC[1][2] BOOT OK in 1:356385822

[30:470806586]HD_IOBNC[1][1] BOOT TRY 0
[30:470825018]card_boot_fpga HD_IOBNC[1][1] BOOT START
[30:470898747]card_boot_fpga HD_IOBNC[1][1] Starting with ID[10b205df]:VER[fac7ff11]
[30:470935611]card_boot_fpga HD_IOBNC[1][1] OLD FAC :VER[1503]
[30:470972476]card_boot_fpga HD_IOBNC[1][1] Loading Factory Bitfile ADDR[00000000]
[30:471027772]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[1]BLK:[2] ADDR=0
[30:540830364]card_boot_fpga HD_IOBNC[1][1] FACTORY IMAGE RECONFIG: SUCCESS
[30:540904092]card_boot_fpga HD_IOBNC[1][1] FACTORY_RRTI_UP:1 TIME:0:00018 
[30:540940957]card_boot_fpga HD_IOBNC[1][1] FACTORY_RECONFIG_OK:1 TIME:0:69839
[30:540977821]card_boot_fpga HD_IOBNC[1][1] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[30:540996253]card_boot_fpga HD_IOBNC[1][1] Loading Application Bitfile ADDR[1080000]
[31:741519726]OLD FACTORY BOOT MODE
[31:802788228]card_boot_fpga HD_IOBNC[1][1] APP IMAGE RECONFIG: SUCCESS
[31:802843524]card_boot_fpga HD_IOBNC[1][1] APP_RRTI_UP:1 TIME:0:00018 
[31:802880388]card_boot_fpga HD_IOBNC[1][1] APP_RECONFIG_OK:1 TIME:1:261755
[31:802917253]card_boot_fpga HD_IOBNC[1][1] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[31:802954117]HD_IOBNC[1][1] BOOT OK in 1:332165963

[31:802990981]HD_IOBNC[1][0] BOOT TRY 0
[31:803009414]card_boot_fpga HD_IOBNC[1][0] BOOT START
[31:803083142]card_boot_fpga HD_IOBNC[1][0] Starting with ID[10b105df]:VER[fac7ff11]
[31:803120006]card_boot_fpga HD_IOBNC[1][0] OLD FAC :VER[1503]
[31:803156871]card_boot_fpga HD_IOBNC[1][0] Loading Factory Bitfile ADDR[00000000]
[31:803212167]ru_reconfig FACTORY SELECT FACTORY L:[1]D:[0]BLK:[2] ADDR=0
[31:869641673]card_boot_fpga HD_IOBNC[1][0] FACTORY IMAGE RECONFIG: SUCCESS
[31:869696970]card_boot_fpga HD_IOBNC[1][0] FACTORY_RRTI_UP:1 TIME:0:00000 
[31:869733834]card_boot_fpga HD_IOBNC[1][0] FACTORY_RECONFIG_OK:1 TIME:0:66466
[31:869770699]card_boot_fpga HD_IOBNC[1][0] FPGA RUNNING[fac7ff11] EXPECTED[fac7ff11]
[31:869807563]card_boot_fpga HD_IOBNC[1][0] Loading Application Bitfile ADDR[1080000]
[33:70386333]OLD FACTORY BOOT MODE
[33:137479397]card_boot_fpga HD_IOBNC[1][0] APP IMAGE RECONFIG: SUCCESS
[33:137553125]card_boot_fpga HD_IOBNC[1][0] APP_RRTI_UP:1 TIME:0:00018 
[33:137589990]card_boot_fpga HD_IOBNC[1][0] APP_RECONFIG_OK:1 TIME:1:267653
[33:137626854]card_boot_fpga HD_IOBNC[1][0] FPGA RUNNING[aaaaaa10] EXPECTED[aaaaaa10]
[33:137645286]HD_IOBNC[1][0] BOOT OK in 1:334654305

[33:184057466]HD_IOBNC[1] HOST_RESET SUCCESS TRY=1 r=0
[33:184112762]HD_IOBNC[1] BOOTED ALL 3 FPGAS OK took 4:334654305
[33:184241788]##############BOARD CALIBRATING
[33:184260220]##############LANE SLOT ENABLE NOT AVAILABLE
[33:184297084]HD_IOBNC[1] START PMA INIT UNDI:18 FCL:6 C2C:6
[33:184333948]HD_IOBNC[1]  UNDI:18 FCL:6 C2C:6
[33:184352381]do_card_boot_pma_init HD_IOBNC[1] set_undi_xcvr_mode
[33:184370813]set_fcb_undi_xcvr_data_mode[1]board_undi_chans:18
[33:185052803]set_fcb_undi_xcvr_data_mode out
[33:185071235]do_card_boot_pma_init HD_IOBNC[1]set_board_undi_xcvr_data_mode 
[33:185089667]set_board_undi_xcvr_data_mode[1] HD_IOBNC:chans:undi:18
[33:186527375]set_board_undi_xcvr_data_mode[1] HD_IOBNC: out r=0
[33:186564240]do_card_boot_pma_init HD_IOBNC[1]set_fcl_igr_mode 
[33:186582672]set_fightclub_igr_eyeq_mode[1] frame FCL chans:16
[33:187043476]set_fightclub_igr_eyeq_mode out
[33:187061908]do_card_boot_pma_init HD_IOBNC[1] set_fcl_egr_mode
[33:187098772]set_fightclub_egr_eyeq_mode[1] BOARD FCL chans:6
[33:187301526]set_fightclub_egr_eyeq_mode out
[33:187319958]set_c2c_eyeq_mode[1]board_c2c_chans:6
[33:187707034]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) INGRESS
[33:187725466]setup_board_fcl_fpga_xcvr_pma[1] HD_IOBNC:chans:fcl:6
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 20 fcl igr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:197992179]ultrix_2ns_set_fcl_S5_pma_rx [1][0] fcl igr rx 00
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn 11 fcl igr rx 00 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 20 fcl igr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:218599335]ultrix_2ns_set_fcl_S5_pma_rx [1][2] fcl igr rx 02
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn 10 fcl igr rx 02 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 22 fcl igr tx 03 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 20 fcl igr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:249731254]ultrix_2ns_set_fcl_S5_pma_rx [1][4] fcl igr rx 04
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  9 fcl igr rx 04 rx_dc 01 rx_eq 08
[33:259979535]setup_board_fcl_fpga_xcvr_pma (do_fcl_push_pma) EGRESS 
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  6 fcl egr rx 00 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn 11 fcl egr tx 00 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  6 fcl egr rx 02 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn 10 fcl egr tx 02 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  7 fcl egr rx 03 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  6 fcl egr rx 04 rx_dc 01 rx_eq 08
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  9 fcl egr tx 04 tx_vod 40 tx_pe0 -2 tx_pe1 00 tx_pe2 08 
[33:341191634]setup_board_fcl_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[33:341228498]setup_board_c2c_fpga_xcvr_pma[1] HD_IOBNC:chans:c2c:6
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 22 c2c tx 00 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  6 c2c rx 00 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 24 c2c tx 01 tx_vod 40 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  7 c2c rx 01 rx_dc 00 rx_eq 06
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 22 c2c tx 02 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  6 c2c rx 02 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 24 c2c tx 03 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  7 c2c rx 03 rx_dc 00 rx_eq 02
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 22 c2c tx 04 tx_vod 40 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  6 c2c rx 04 rx_dc 00 rx_eq 06
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 24 c2c tx 05 tx_vod 35 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  7 c2c rx 05 rx_dc 00 rx_eq 02
[33:465037320]setup_board_c2c_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[33:465055752]setup_board_undi_fpga_xcvr_pma[1] HD_IOBNC:chans:undi:18
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 12 undi igr tx 00 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 18 undi igr tx 01 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 14 undi igr tx 02 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 16 undi igr tx 03 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 11 chn 18 undi igr tx 04 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  2 blk 10 chn 20 undi igr tx 05 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 12 undi igr tx 06 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 18 undi igr tx 07 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 14 undi igr tx 08 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 16 undi igr tx 09 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 11 chn 18 undi igr tx 10 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  1 blk 10 chn 20 undi igr tx 11 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 18 undi igr tx 12 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 12 undi igr tx 13 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 14 undi igr tx 14 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 10 chn 20 undi igr tx 15 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 16 undi igr tx 16 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  1 dev  0 blk 11 chn 18 undi igr tx 17 tx_vod 30 tx_pe0 -3 tx_pe1 00 tx_pe2 01 
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  2 undi egr rx 00 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  4 undi egr rx 01 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  3 undi egr rx 02 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  4 undi egr rx 03 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 11 chn  5 undi egr rx 04 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  2 blk 10 chn  5 undi egr rx 05 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  2 undi egr rx 06 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  4 undi egr rx 07 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  3 undi egr rx 08 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  4 undi egr rx 09 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 11 chn  5 undi egr rx 10 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  1 blk 10 chn  5 undi egr rx 11 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  2 undi egr rx 12 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  3 undi egr rx 13 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  4 undi egr rx 14 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 10 chn  5 undi egr rx 15 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  4 undi egr rx 16 rx_dc 00 rx_eq 01
set_s5_gxb_rx_pma lane  1 dev  0 blk 11 chn  5 undi egr rx 17 rx_dc 00 rx_eq 03
[33:836684970]setup_board_undi_fpga_xcvr_pma[1] HD_IOBNC: out r=0
[33:836721835]setup_fcb_undi_fpga_xcvr_pma[1] frame_FCB_undi_chans:12 undi(8) fclx(4) 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  0 undi igr tx 00 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  6 undi igr tx 01 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  2 undi igr tx 02 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  6 undi igr tx 03 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  4 undi igr tx 04 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn 11 undi igr tx 05 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  8 undi igr tx 06 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  0 undi igr tx 07 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  1 undi igr tx 08 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 10 chn  7 undi igr tx 09 tx_vod 31 tx_pe0 00 tx_pe1 00 tx_pe2 01 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  4 undi igr tx 10 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_tx_pma lane  0 dev  0 blk 11 chn  7 undi igr tx 11 tx_vod 30 tx_pe0 00 tx_pe1 00 tx_pe2 00 
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  0 undi egr rx 00 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  6 undi egr rx 01 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  0 undi egr rx 02 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  6 undi egr rx 03 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  4 undi egr rx 04 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn 11 undi egr rx 05 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  8 undi egr rx 06 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  2 undi egr rx 07 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  1 undi egr rx 08 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 10 chn  7 undi egr rx 09 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  4 undi egr rx 10 rx_dc 00 rx_eq 08
set_s5_gxb_rx_pma lane  0 dev  0 blk 11 chn  7 undi egr rx 11 rx_dc 00 rx_eq 08
[34:81961729]setup_fcb_undi_fpga_xcvr_pma[1] ULTRIX_2NS: out r=0
[34:81998594]setup_board_undi_xpt_chan_pma 1
[34:82017026]setup_board_undi_xpt_chan_pma 1 IGR
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1e val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1c val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 16 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 17 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page e val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 14 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page d val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 6 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 0 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 2 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 3 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 10 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 23 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 1a val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 22 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 12 val 59 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page 18 val 59 r=0
[34:84855578]setup_board_undi_xpt_chan_pma 2NS LN[1] FCLX RX chan 
maxp160_channel_pma  L0:D0:BLK150:ADR=9 RX eq1 01 eq0 25  page c val 59 r=0
[34:85058332]setup_board_undi_xpt_chan_pma 2NS FCLX RX [1] eq1 01 eq0 25 MAP=012
[34:85095196]setup_board_undi_xpt_chan_pma 1 EGR
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 42     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 48     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 41     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 38     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3a     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 32     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 9a     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 49     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 43     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 18     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 3b     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 12     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 01     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 52     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 09     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 11     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 00     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 62     hwval 5 r=0
maxp160_channel_pma  L0:D0:BLK150:ADR=12  TX sw_drv 05 td2x_drv 00  page 90     hwval 5 r=0
[34:86883116]setup_board_undi_xpt_chan_pma 2NS FCLX TX [1] sw_drv 05 td2x_drv 00  MAP=003
[34:86938413]HD_IOBNC[1] do_card_boot_pma_init OUT r=0 SUCCESS
rrtiddr_iobnc_ddr_init[1] IN
DDR CALIBRATE[1][0] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][0] DONE ret=(0) PASS
DDR CALIBRATE[1][1] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][1] DONE ret=(0) PASS
DDR CALIBRATE[1][2] DONE ret=(0) PASS
rrtiddr_audio_lvds_check AUD_LVDS CHK ON [0]
DDR AUDIO PLL[1][2] DONE ret=(0) PASS
rrti_data_test lane 1 dev 2 blk 1  addr 16 sz=496 timeout 250
RRTI BIST PASS: Lane:1 Board:IOBNC EndDevice:2
FPGA_STATUS:APPLICATION
[01][0][IOBNC]10b112cc:aaaaaa10
[01][1][IOBNC]10b212cc:aaaaaa10
[01][2][IOBNC]10b212cc:aaaaaa10
[34:812852187]##############BOARD HW READY
[34:812889051]##############BOARD ONLINE
[34:812907483][1]:HD_IOBNC Starting Monitor Loop
